This invention relates generally to EPROM and EEPROM operating techniques. Specifically, the invention relates to a biasing technique for improving the programmability of EPROMs and EEPROMs and for allowing further process scaling.
As with many other areas of integrated electronics, manufacturers of EPROMs and EEPROMs strive to produce components having smaller and smaller sizes. Achieving smaller size enables more components to be placed within a given area of a wafer, thereby increasing yields and lowering costs. As process dimensions scale to smaller sizes, however, internal voltage fields within the semiconductor chip must also scale. Scaling these voltage fields is necessary to reduce field stress on gate oxides and junctions, and to maintain field isolation, especially between adjacent diffusions of bit lines.
The meaning of the term `programming` as used herein needs to be clarified at the outset. For conventional EPROMs, to `program` a memory transistor is to place a normally low threshold memory transistor at a high threshold. For EEPROMs, some parties have used `erasing` where others use `programming`. Hereafter, for EEPROMs, `programming` refers to placing a high threshold memory transistor at a low threshold.
FIG. 1 is a schematic diagram of a portion of a conventional EPROM or EEPROM array employing conventional programming biasing. This array portion includes bit lines 10 and 20, memory transistors 30 and 40, polysilicon word lines 50-53, metal or diffused lines 60 and 61. A particular memory cell is programmed by bringing both its associated word line and bit line to potential Vpp. Lines 60 and 61 are coupled to ground. Typical CMOS drain programming voltage Vpp is about 2.5 times the read voltage Vcc. Thus, typical voltages for Vpp and Vcc are about 12.5 V and 5 V, respectively. Bit lines with memory cells not selected for programming are connected to ground, or 0 V. As shown in FIG. 1, to program cell 30, word line 50 and bit line 10 are placed at potential Vpp, selecting memory cell 30 for programming. Bit line 20 is grounded, so memory transistor 40 will not be programmed. Depending upon the physical layout of the circuit, a parasitic transistor, with bit lines 10 and 20 as drain and source and word line 50 as gate, can be turned on, potentially adversely affecting operation.
Such a parasitic transistor is especially likely to be formed in an EEPROM employing dual bit lines, because the dual bit lines tend to be spaced more closely together, often separated by only a line width. This phenomenon is illustrated in FIGS. 2 and 3. FIG. 2 is a top view which illustrates the parasitic transistor between dual bit lines of an EEPROM. If a memory cell associated with write bit line 100, read bit line 110, and word line 120 is to be programmed, write bit line 100 conventionally will be brought to Vpp, read bit line 110 to ground (0 V), and word line 120 to Vpp. The undesired parasitic MOS transistor 130 can then be formed by word line 120, coupling bit lines 100 and 110. Because write bit line 100 is generally coupled to a high impedance voltage source, draining even a small amount of current through parasitic transistor 130 to bit line 110 can disrupt circuit operation.
Wherever parasitic transistors may appear, they generally take a form similar to that illustrated in FIG. 3, which is a cross-sectional view of a typical parasitic transistor 200 as formed between two memory cells 201 and 202. Parasitic transistor 200, lying in a P' substrate, includes two column diffusion N.sup.+ junctions 210 and 220, which are parts of memory cells 201 and 202 and which serve as drain and source to parasitic transistor 200. Under conventional programming biasing, junction 210 could be at Vpp and junction 220 at 0 V. Separating junctions 210 and 220 is a region 230 of field oxide, typically silicon dioxide underneath which lies field region 240, which has been doped with boron to help prevent inversion. Field region 240 cannot be too heavily doped, however, for this doping decreases the junction breakdown voltage Vbj of the active transistors at either side. Lying atop field oxide region 230 is a polysilicon layer 250, such as from a word line, which forms the gate for the parasitic transistor. During programming, this gate 250 may carry Vpp, which could cause field inversion in field region 240, coupling well 210 to well 220.
A variety of techniques have been employed in the prior art in response to the problems that accompany smaller sizes. One of these has been to simply scale down the programming voltage; however, this can be done only so far. Non-volatile technologies such as EPROMs and EEPROMs are particularly sensitive to programming voltage level. Voltage scaling places even more stringent requirements upon process and cell design, and may adversely affect manufacturing margins. Another technique has been to decouple programming circuits, which employ the highest voltage levels, from high speed circuits by use of separate gate oxides and design rules. Use of additional oxide thickness for programming transistors increases process complexity, which is undesirable. Other techniques for prevention of field inversion have been greater isolation spacing and greater field doping levels. However, increasing isolation spacing is contrary to decreasing size, and as mentioned, increasing field doping levels decreases junction breakdown voltages.
What is needed is a technique for building fast and dense EPROM and EEPROM circuits with adequate programming margins for gate oxide stress and field isolation.